TECIP

Events/Seminars

Il 25.10.2016

Cache Persistence Aware WCRT Analysis for Fixed Priority Preemptive Systems

BY Dr. Geoffrey Nelissen – Research Center in Real-Time and Embedded Computing Systems (CISTER), Porto, Portugal

Blue Room – TeCIP Institute

The introduction of caches in modern computing platforms is the cause of important variations in the execution time of each task, depending on whether the instruction and data it requires are already loaded in the cache or not. Many works have focused on analyzing the impact of preemptions on the worst-case execution time (WCET) and worst-case response time (WCRT) of tasks in preemptive systems.

Short Bio:

Geoffrey Nelissen earned his M.Sc. degree in Electrical Engineering at Université Libre de Bruxelles, Belgium, in 2008. He then worked during four years as a Ph.D. student in the PARTS research unit of ULB. In 2012, he received his Ph.D. degree under the supervision of Professors Joël Goossens and Dragomir Milojevic, on the topic "Efficient Optimal Multiprocessor Scheduling Algorithms for Real-Time Systems". He is currently workin g at CISTER, Porto, Portugal, as a research scientist in the area of real-time scheduling, embedded, distributed and safety critical system design and analysis.

ATTACHMENTS

geoffrey_nelissen.pdf
File PDF - 266 kb

INFO:

Seminar

Dates:
Il 25.10.2016

Timetables:
From 16:00

Event's place:
Italy
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