Outstanding Paper Award at RTAS 2026 for research on the predictable acceleration of deep neural networks.
An important international recognition for the research carried out at the Scuola Superiore Sant’Anna has come from the 32nd edition of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2026), one of the world’s leading scientific conferences on embedded systems and time-constrained applications, held in Saint-Malo, France, from May 12 to 14, 2026.
RTAS is a major reference forum for the international scientific community working on time-critical systems, namely systems in which correctness and reliability also depend on meeting precise timing constraints. The conference features contributions on methodologies, tools, algorithms, and hardware and software innovations for the design, implementation, and verification of systems with stringent timing requirements.
In this context, the paper entitled “Time-Predictable Acceleration of Deep Neural Networks on FPGA SoCs with Multi-Core DPUs” received the Outstanding Paper Award, a recognition reserved for contributions of the highest quality and scientific impact.
The study was authored by Federico Aromolo, Niko Salamini, Jacopo Del Granchio, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo, faculty members and researchers of the ReTiS (Real-Time Systems Laboratory) at the TeCIP Institute (Telecommunications, Computer Engineering and Photonics) of the Scuola Superiore Sant’Anna.
The research addresses one of the key challenges in integrating artificial intelligence into critical cyber-physical systems: ensuring that deep neural networks can operate while meeting strict and predictable timing constraints. Applications such as autonomous vehicles, industrial robotics, and medical devices require not only high computational performance, but also the ability to guarantee deterministic response times.
The work proposes an innovative framework that enables neural networks to operate with predictable response times on FPGA (Field-Programmable Gate Array)-based platforms, reconfigurable hardware devices particularly well suited for these applications, using DPUs (Deep Learning Processing Units) as dedicated accelerators for AI processing. The approach combines techniques to control and optimize memory access with advanced real-time scheduling methods, making it possible to rigorously guarantee execution times without sacrificing high performance or energy efficiency.
The results demonstrate how multi-core DPU-based architectures, namely systems using multiple AI-dedicated processing units capable of operating in parallel, can represent an effective solution for combining high-performance AI inference with the temporal predictability required in mission-critical systems. The techniques developed therefore contribute to making AI integration safer and more reliable across next-generation application domains, ranging from automotive and industry to robotics and aerospace.
