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Sant'Anna - School of Advanced Studies Pisa

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Full Professor

TeCIP Institute

Giorgio Carlo Buttazzo

Publications

Aromolo, F.; Biondi, A.; Nelissen, G.; Buttazzo, G.

Event-driven delay-induced tasks: Model, analysis, and applications Open new browser tab

(2021)
Casini, Daniel; Biondi, Alessandro; Cicero, Giorgiomaria; Buttazzo, Giorgio

Latency Analysis of I/O Virtualization Techniques in Hypervisor-Based Real-Time Systems Open new browser tab

(2021)
Seyoum, Biruk; Pagani, Marco; Biondi, Alessandro; Buttazzo, Giorgio

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC Open new browser tab

(2021)
Belluardo, L.; Stevanato, A.; Casini, D.; Cicero, G.; Biondi, A.; Buttazzo, G.

A Multi-Domain Software Architecture for Safe and Secure Autonomous Driving Open new browser tab

(2021)
Casini, D.; Pazzaglia, P.; Biondi, A.; Di Natale, M.; Buttazzo, G.

Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks Open new browser tab

(2020)
Restuccia, Francesco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio

Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC Open new browser tab

(2020)
Restuccia, F.; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.

Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs Open new browser tab

(2020)
Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G.

AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC Open new browser tab

(2020)
Casini, D.; Biondi, A.; Nelissen, G.; Buttazzo, G.

A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling Open new browser tab

(2020)
Casini, Daniel; Biondi, Alessandro; Nelissen, Geoffrey; Buttazzo, Giorgio

Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions Open new browser tab

(2019)