Usage of a robot to service slide gates of casting ladles Open new browser tab Colla, V.; Matino, R.; Faes, A.; Schivalocchi, M.; Romaniello, L.; Schroder, A. (2020)
Ultrafast, Zero-Bias, Graphene Photodetectors with Polymeric Gate Dielectric on Passive Photonic Waveguides Open new browser tab Miseikis, V.; Marconi, S.; Giambra, M. A.; Montanaro, A.; Martini, L.; Fabbri, F.; Pezzini, S.; Piccinini, G.; Forti, S.; Terres, B.; Goykhman, I.; Hamidouche, L.; Legagneux, P.; Sorianello, V.; Ferrari, A. C.; Koppens, F. H. L.; Romagnoli, M.; Coletti, C. (2020)
Is OpenCL Driven Reconfigurable Hardware Suitable for Virtualising 5G Infrastructure? Open new browser tab Civerchia, F.; Pelcat, M.; Maggiani, L.; Kondepu, K.; Castoldi, P.; Valcarenghi, L. (2020)
Control of open and disaggregated transport networks using the Open Network Operating System (ONOS) [Invited] Open new browser tab Sgambelluri, A.; Casellas, R.; Morro, R.; Campanella, A.; Castoldi, P.; Giorgetti, A. (2020)
Network Slicing in SDN networks Open new browser tab Scano, D.; Valcarenghi, L.; Kondepu, K.; Castoldi, P.; Giorgetti, A. (2020)
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs Open new browser tab Seyoum, Biruk B.; Pagani, Marco; Biondi, Alessandro; Balleri, Sara; Buttazzo, Giorgio (2020)
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling Open new browser tab Casini, D.; Biondi, A.; Nelissen, G.; Buttazzo, G. (2020)
Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks Open new browser tab Casini, D.; Pazzaglia, P.; Biondi, A.; Di Natale, M.; Buttazzo, G. (2020)
AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC Open new browser tab Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G. (2020)
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs Open new browser tab Restuccia, F.; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G. (2020)