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Sant'Anna - School of Advanced Studies Pisa

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Full Professor

TeCIP Institute

Giorgio Carlo Buttazzo

Publications

Seyoum, Biruk B.; Pagani, Marco; Biondi, Alessandro; Balleri, Sara; Buttazzo, Giorgio

Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs Open new browser tab

(2020)
Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G.

AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC Open new browser tab

(2020)
Casini, D.; Biondi, A.; Nelissen, G.; Buttazzo, G.

A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling Open new browser tab

(2020)
Casini, Daniel; Biondi, Alessandro; Nelissen, Geoffrey; Buttazzo, Giorgio

Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions Open new browser tab

(2019)
Casini, Daniel; Biondi, Alessandro; Nelissen, Geoffrey; Buttazzo, Giorgio

Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures Open new browser tab

(2019)
Pagani, M.; Rossi, E.; Biondi, A.; Marinoni, M.; Lipari, G.; Buttazzo, G.

A bandwidth reservation mechanism for axi-based hardware accelerators on FPGAs Open new browser tab

(2019)
Biondi, Alessandro; Nesti, Federico; Cicero, Giorgiomaria; Casini, Daniel; Buttazzo, Giorgio Carlo

A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems Open new browser tab

(2019)
Seyoum, B. B.; Biondi, A.; Buttazzo, G. C.

Flora: Floorplan optimizer for reconfigurable areas in FPGAs Open new browser tab

(2019)
Restuccia, Francesco; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.

Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs Open new browser tab

(2019)
Casini, D.; Biondi, A.; Buttazzo, G.

Analyzing parallel real-time tasks implemented with thread pools Open new browser tab

(2019)